1. Field of the Invention
The present invention relates to integrated circuit technology. More particularly, the present invention relates to electrically programmable interconnect technology and to electrically programmable interconnect elements suitable for fabrication as a part of a fabrication process for integrated circuits, hybrids, multichip modules, and interconnect structures on insulating or conductive substrates and the like. Still more particularly, and according to a first aspect of this invention, it relates to the field of integrated two-terminal fuse-antifuse ("Ab-fuse") structures used in one-time field programmable electrically programmable circuits contained in such integrated circuit devices. Still more particularly, and according to a second aspect of this invention, it relates to the incorporation of air gaps in fuse and fuse-antifuse structures for improved reliability of the programmed fuses and fuse-antifuses.
2. The Prior Art
Numerous schemes for providing integrated circuit interconnections are known in the prior art. Various ones of these schemes relate to electrically programmable interconnections for use in integrated circuits, wherein a plurality of potential interconnection points are fabricated into an integrated circuit during the manufacturing process, but the particular interconnections between circuit nodes in the integrated circuit are made by the user by electrically programming selected ones of the interconnections so that desired connections between circuit nodes are made while other potential interconnections are deliberately unrealized.
There are several types of electrically programmable interconnect schemes which are currently available to the integrated circuit user. One type of electrically programmable interconnect is reprogrammable, and can be altered by a user after initial circuit configuration has been accomplished. This type of interconnect may be implemented by simple transistors whose gate voltages are controlled to determine the interconnections to be made, or by one form or another of non-volatile memory devices, such as EPROMS, EEPROMS, NOVRAMS, or combinations of both simple transistors and non-volatile memory elements. An example of a technology for implementing this type of interconnect is found in U.S. Pat. No. 4,870,302 to Freeman.
Another type of electrically programmable interconnection is one-time programmable, and once initially configured, may not be reconfigured. The most popular examples of this type of electrically programmable interconnect may take one of two forms, a first form, normally short circuited until rendered an open circuit as a result of a programming procedure, and a second form normally open circuited until rendered a short circuit as a result of a programming procedure.
The first form of one-time electrically programmable interconnect is usually referred to as fuse technology, and is exemplified by the disclosure found in U.S. Pat. No. 4,796,075 to Whitten. The second form of one-time electrically programmable interconnect is usually referred to as "antifuse" technology, and is exemplified by the disclosures found in U.S. Pat No. 4,823,181 to Mohsen et al., U.S. Pat No. 4,899,205 to Hamdy et al., and European Patent Application No. 90309731.9, Publication No. 0 416 903 A2, to Whitten et al.
While each form of one-time electrically programmable interconnect technology has been and continues to be useful in numerous integrated circuit applications, there remains room for improvement of this technology. For example, interconnect networks comprising fuse technology initially present a network of connected nodes. Fuses connecting unwanted circuit paths are then programmed by applying a voltage or current source across them. One disadvantage of this method is that other fuses in the interconnection network which are not to be programmed are in the current path of the fuse to be programmed. Depending on the configuration of the particular network, these "sneak" paths for current can be significant enough to require a large amount of current to be supplied to program the desired fuses. Typically, blocking diodes are employed to eliminate sneak paths. Blocking diodes require a semiconductor substrate in which to form the diode and add to the area and complexity of the integrated circuit device containing them.
When antifuse technology is used, care must be taken to avoid the inadvertent programming of antifuses which are intended to remain unprogrammed. In some cases, the existence of parallel current and voltage paths through the potential interconnection networks raises the possibility of stressing antifuses which are to remain unprogrammed. Overly stressed antifuses may inadvertently become programmed, or may become so weakened that they will present a reliability problem and shorten the operating lifetime of the circuit in which they are used. This consideration necessitates careful design of the programming process and may also affect circuit design considerations.
Fuses have been widely used in integrated circuits as electrically programmable elements for providing a variety of functions including, for example, programmable logic devices, circuit redundancy circuits and circuit trimming. There are two structures of fuses commonly used in integrated circuits: the first structure embodies a patterned conductor film which is embedded between two dielectric layers; the second structure embodies a patterned conductor film with the top-side of the fuse exposed (no dielectric protection). The former structure has often been used in electrically programmable products such as Proms and PALs, while the latter structure is often found in analog circuit products for circuit trimming, or in memory circuit products for circuit redundancy.
In the case of PROMs or PALs, fuses are typically used as pull-downs in the transistor array, hence, only moderately low resistance is needed to pull the gates to ground (typically in the range of 25 to 75 ohms). In such applications the metal film fuses may be constructed to open under the dielectric upon application of a moderate programming current across the fuse terminals (typically tens of milliamperes). Since the fuse thickness in this application is thin (on the order of a few hundred angstroms thick) in comparison to the overlaying dielectric (which is typically one to several microns thick) and the fuse width is moderate (typically on the order of about 2 microns wide), the dielectric remains intact after fuse programming, even though the fuse material is redistributed during the fuse programming event.
Turning now to the drawings, FIGS. 1 and 2 depict, respectively, a top and a cross-sectional view of a conventional horizontal blowable fuse 10 according to the prior art. The structure is built over a substrate 11 which is a silicon wafer comprising a p-type silicon substrate 11a and an n-type epitaxial silicon layer 11b. An n.sup.+ -type buried layer 11c, a p-type base region 11d and an n.sup.+ -type emitter region 11e are formed in the substrate. An oxide layer 13 is deposited over the substrate 11. A first via 24 is opened in oxide layer 13 and conductive fuse material layer 26 is deposited which comprises fuse neck 12 as shown in FIG. 1. A metallization layer 15 is then deposited to provide electrical contacts to the fuse structure 10. An oxide interlayer dielectric layer 17 is then disposed over the structure 10. Additional metal interconnect layers may then be constructed. In this device there is no air gap above, below or surrounding fuse neck 12. Interlayer dielectric oxide layer 17 is in direct contact with the fuse material at fuse neck 12. As a result, if the fuse material is more than a few hundred angstroms thick or wider than a few .mu.m, then oxide layer 17 may suffer melting or other disruption during the blowing of fuse 10 at fuse neck 12 during a programming operation and, if the energy dissipated in the fuse blowing incident is sufficient, oxide layer 17 may be cracked, broken or otherwise destroyed rendering the device at least partially inoperative.
While fuses are well known in the prior art, there is a need for a compact, two-terminal Ab-fuse which has an "ON" resistance of less than 2 ohms. Such a device, connected between two circuit nodes, initially does not provide an electrical connection between the two circuit nodes. It may then be programmed with a voltage to blow the "A-fuse" (antifuse), causing it to conduct between the two circuit nodes. Then, upon application of a current between the two circuit nodes, the fuse portion or "B-fuse" (blowable fuse) will blow, making the device permanently non-conductive.
There is also a need in the art for a method of constructing a B-fuse or the B-fuse portion of an Ab-fuse so that in a high current programming event, it does not damage the integrated circuit. A desirable technique is to incorporate isolation between the B-fuse and the dielectric layer, in the form of an air gap, to provide a volume in which disrupted fuse material may dissipate and also provide a physical and thermal isolation between the fuse and the dielectric.
Several prior art patents address the construction of various types of gap-like structures in integrated circuit structures, however, although fit for their intended purposes, these structures do not meet the requirements of providing a low cost method for fabricating a fuse with an air gap between two layers of metal interconnect. Fritzinger et al., U.S. Pat. No. 3,647,585, describes an air gap formed by depositing a conductor over a compressively stressed layer which is in turn over a metal layer which can be under-etched. By under-etching the metal layer until it disappears, the compressive layer will force the upper layers away from the substrate leaving an air gap and breaking any pinhole shorts which may be present. This method requires several complex metal layers and provides an unpassivated bridge structure unsuitable for use with integrated circuit fuses.
Bierig, U.S. Pat. No. 4,032,949, describes a fuse element surrounded by air. The structure is formed by forming three or more layers of chemically dissimilar materials over a region in which the fuse is to be formed. The top layers are then etched away from the region where the fuse is to be formed leaving the lower two layers, the top one of which forms the actual fuse. The lower layer is then etched away leaving the fuse suspended from the underlying substrate. This fuse must be formed on silicon to create the suspended fuse and is thus unacceptable for use between two metal interconnect layers.
Nicolay, U.S. Pat. No. 4,198,744, describes a suspended necked fuse element. A side-etching process is used to excavate the material under the fuse. Nicolay does not provide a method for protecting the fuse from further processing or chemical attack. This passivation protection is required for high reliability integrated circuits.
te Velde et al., U.S. Pat. No. 4,460,914 describes a fuse within a cavity of an integrated circuit structure. An aluminum metal sacrificial layer is used to define the air gap. The aluminum is then coated with a metallization layer of nickel and selectively etched from the side to form a cavity. A passivation layer is then deposited over the nickel metallization layer. This process is not compatible with a top aluminum metallization layer because the sacrificial etch of the aluminum effectively eliminates the possibility of using aluminum as the metallization layer. This is an undesirable outcome as the most common processes today require aluminum as the top metallization layer. te Velde et al., U.S. Pat. No. 4,528,583 is similar to the foregoing, except that an electrostatic switch is constructed in place of the fuse within the air gap.
A prior art programmable memory circuit, which utilizes fuses and antifuses was disclosed in U.S. Pat. No. 4,441,167 to Principi. This patent discloses the use of serially connected fuses and normally high resistance programmable devices in conjunction with an integrated circuit, specifically an emitter follower transistor array. The construction of this device is not suitable for Field Programmable Interconnect Component ("FPIC") devices as it cannot be fabricated at a metal-1 to metal-2 crossover in a programmable array due to the requirement of the presence of active switching devices (i.e., transistors). The present invention is directed to a structure incorporating fuses and antifuses in an economical two (or more) level integrated circuit without the need for transistors or other active devices or substrates.
Accordingly, there is a need in the art for an improved low cost, easy to manufacture, high-current fuse and Ab-fuse structure compatible with standard integrated circuit manufacturing processes and capable of withstanding the forces and trauma associated with high-current programming while still providing low-resistance signal paths across its terminals when in a short-circuit state.